1. Technical Field
The present invention relates to a demodulation apparatus, a test apparatus, and an electronic device. In particular, the present invention relates to a demodulation apparatus that demodulates an amplitude-phase-modulated signal, and to a test apparatus and an electronic device for testing a device under test that outputs the amplitude-phase-modulated signal as an output signal.
2. Related Art
Along with an increase in the circuit density and operational speed of semiconductors, the amount of data transmitted within a semiconductor has also increased dramatically. However, the amount of data transmitted out from a semiconductor has not increased as much as the amount of data transmitted within the semiconductor due to restrictions on the number of pins, shape, wiring, and the like. This leads to a problem of an increased gap between the amount of data transmitted within the semiconductor and the amount of data transmitted outside of the semiconductor.
In Sunil Jain, “GHz Interconnects—Electrical Aspects”, International Test Conference NOTES Tutorial 3, (US), Oct. 22, 2006, p. 27, a technique is disclosed for performing data transmission between semiconductors using an amplitude-phase-modulated signal having a transition phase and a level selected from among a plurality of transition phases and levels according to the transmitted data. With such an amplitude-phase-modulated signal, the multiple bits of data can be transmitted in a single period, thereby decreasing the gap between external and internal data transmission in a semiconductor.
In the case of a system that transmits an amplitude-phase-modulated signal without transmitting a clock signal in parallel, the receiving apparatus must recover the clock signal from the received amplitude-phase-modulated signal. However, the transition phase and the amplitude of the amplitude-phase-modulated signal fluctuates for each symbol according to the transmission data. Accordingly, even if the amplitude-phase-modulated signal is input as-is to the PLL, the clock signal output by the PLL will include an error caused by the phase fluctuation corresponding to the transmission data.